hciattach_intel.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. *
  4. * BlueZ - Bluetooth protocol stack for Linux
  5. *
  6. * Copyright (C) 2012 Intel Corporation. All rights reserved.
  7. *
  8. *
  9. */
  10. #ifdef HAVE_CONFIG_H
  11. #include <config.h>
  12. #endif
  13. #define _GNU_SOURCE
  14. #include <stdio.h>
  15. #include <stdlib.h>
  16. #include <unistd.h>
  17. #include <string.h>
  18. #include <errno.h>
  19. #include <fcntl.h>
  20. #include <sys/param.h>
  21. #include <sys/ioctl.h>
  22. #include <time.h>
  23. #include "lib/bluetooth.h"
  24. #include "lib/hci.h"
  25. #include "lib/hci_lib.h"
  26. #include "hciattach.h"
  27. #ifdef INTEL_DEBUG
  28. #define DBGPRINT(fmt, args...) printf("DBG: " fmt "\n", ## args)
  29. #define PRINT_PACKET(buf, len, msg) { \
  30. int i; \
  31. printf("%s\n", msg); \
  32. for (i = 0; i < len; i++) \
  33. printf("%02X ", buf[i]); \
  34. printf("\n"); \
  35. }
  36. #else
  37. #define DBGPRINT(fmt, args...)
  38. #define PRINT_PACKET(buf, len, msg)
  39. #endif
  40. #define PATCH_SEQ_EXT ".bseq"
  41. #define PATCH_FILE_PATH "/lib/firmware/intel/"
  42. #define PATCH_MAX_LEN 260
  43. #define PATCH_TYPE_CMD 1
  44. #define PATCH_TYPE_EVT 2
  45. #define INTEL_VER_PARAM_LEN 9
  46. #define INTEL_MFG_PARAM_LEN 2
  47. /**
  48. * A data structure for a patch entry.
  49. */
  50. struct patch_entry {
  51. int type;
  52. int len;
  53. unsigned char data[PATCH_MAX_LEN];
  54. };
  55. /**
  56. * A structure for patch context
  57. */
  58. struct patch_ctx {
  59. int dev;
  60. int fd;
  61. int patch_error;
  62. int reset_enable_patch;
  63. };
  64. /**
  65. * Send HCI command to the controller
  66. */
  67. static int intel_write_cmd(int dev, unsigned char *buf, int len)
  68. {
  69. int ret;
  70. PRINT_PACKET(buf, len, "<----- SEND CMD: ");
  71. ret = write(dev, buf, len);
  72. if (ret < 0)
  73. return -errno;
  74. if (ret != len)
  75. return -1;
  76. return ret;
  77. }
  78. /**
  79. * Read the event from the controller
  80. */
  81. static int intel_read_evt(int dev, unsigned char *buf, int len)
  82. {
  83. int ret;
  84. ret = read_hci_event(dev, buf, len);
  85. if (ret < 0)
  86. return -1;
  87. PRINT_PACKET(buf, ret, "-----> READ EVT: ");
  88. return ret;
  89. }
  90. /**
  91. * Validate HCI events
  92. */
  93. static int validate_events(struct patch_entry *event,
  94. struct patch_entry *entry)
  95. {
  96. if (event == NULL || entry == NULL) {
  97. DBGPRINT("invalid patch entry parameters");
  98. return -1;
  99. }
  100. if (event->len != entry->len) {
  101. DBGPRINT("lengths are mismatched:[%d|%d]",
  102. event->len, entry->len);
  103. return -1;
  104. }
  105. if (memcmp(event->data, entry->data, event->len)) {
  106. DBGPRINT("data is mismatched");
  107. return -1;
  108. }
  109. return 0;
  110. }
  111. /**
  112. * Read the next patch entry one line at a time
  113. */
  114. static int get_next_patch_entry(int fd, struct patch_entry *entry)
  115. {
  116. int size;
  117. char rb;
  118. if (read(fd, &rb, 1) <= 0)
  119. return 0;
  120. entry->type = rb;
  121. switch (entry->type) {
  122. case PATCH_TYPE_CMD:
  123. entry->data[0] = HCI_COMMAND_PKT;
  124. if (read(fd, &entry->data[1], 3) < 0)
  125. return -1;
  126. size = (int)entry->data[3];
  127. if (read(fd, &entry->data[4], size) < 0)
  128. return -1;
  129. entry->len = HCI_TYPE_LEN + HCI_COMMAND_HDR_SIZE + size;
  130. break;
  131. case PATCH_TYPE_EVT:
  132. entry->data[0] = HCI_EVENT_PKT;
  133. if (read(fd, &entry->data[1], 2) < 0)
  134. return -1;
  135. size = (int)entry->data[2];
  136. if (read(fd, &entry->data[3], size) < 0)
  137. return -1;
  138. entry->len = HCI_TYPE_LEN + HCI_EVENT_HDR_SIZE + size;
  139. break;
  140. default:
  141. fprintf(stderr, "invalid patch entry(%d)\n", entry->type);
  142. return -1;
  143. }
  144. return entry->len;
  145. }
  146. /**
  147. * Download the patch set to the controller and verify the event
  148. */
  149. static int intel_download_patch(struct patch_ctx *ctx)
  150. {
  151. int ret;
  152. struct patch_entry entry;
  153. struct patch_entry event;
  154. DBGPRINT("start patch downloading");
  155. do {
  156. ret = get_next_patch_entry(ctx->fd, &entry);
  157. if (ret <= 0) {
  158. ctx->patch_error = 1;
  159. break;
  160. }
  161. switch (entry.type) {
  162. case PATCH_TYPE_CMD:
  163. ret = intel_write_cmd(ctx->dev,
  164. entry.data,
  165. entry.len);
  166. if (ret <= 0) {
  167. fprintf(stderr, "failed to send cmd(%d)\n",
  168. ret);
  169. return ret;
  170. }
  171. break;
  172. case PATCH_TYPE_EVT:
  173. ret = intel_read_evt(ctx->dev, event.data,
  174. sizeof(event.data));
  175. if (ret <= 0) {
  176. fprintf(stderr, "failed to read evt(%d)\n",
  177. ret);
  178. return ret;
  179. }
  180. event.len = ret;
  181. if (validate_events(&event, &entry) < 0) {
  182. DBGPRINT("events are mismatched");
  183. ctx->patch_error = 1;
  184. return -1;
  185. }
  186. break;
  187. default:
  188. fprintf(stderr, "unknown patch type(%d)\n",
  189. entry.type);
  190. return -1;
  191. }
  192. } while (1);
  193. return ret;
  194. }
  195. static int open_patch_file(struct patch_ctx *ctx, char *fw_ver)
  196. {
  197. char patch_file[PATH_MAX];
  198. snprintf(patch_file, PATH_MAX, "%s%s%s", PATCH_FILE_PATH,
  199. fw_ver, PATCH_SEQ_EXT);
  200. DBGPRINT("PATCH_FILE: %s", patch_file);
  201. ctx->fd = open(patch_file, O_RDONLY);
  202. if (ctx->fd < 0) {
  203. DBGPRINT("cannot open patch file. go to post patch");
  204. return -1;
  205. }
  206. return 0;
  207. }
  208. /**
  209. * Prepare the controller for patching.
  210. */
  211. static int pre_patch(struct patch_ctx *ctx)
  212. {
  213. int ret, i;
  214. struct patch_entry entry;
  215. char fw_ver[INTEL_VER_PARAM_LEN * 2];
  216. DBGPRINT("start pre_patch");
  217. entry.data[0] = HCI_COMMAND_PKT;
  218. entry.data[1] = 0x11;
  219. entry.data[2] = 0xFC;
  220. entry.data[3] = 0x02;
  221. entry.data[4] = 0x01;
  222. entry.data[5] = 0x00;
  223. entry.len = HCI_TYPE_LEN + HCI_COMMAND_HDR_SIZE + INTEL_MFG_PARAM_LEN;
  224. ret = intel_write_cmd(ctx->dev, entry.data, entry.len);
  225. if (ret < 0) {
  226. fprintf(stderr, "failed to send cmd(%d)\n", ret);
  227. return ret;
  228. }
  229. ret = intel_read_evt(ctx->dev, entry.data, sizeof(entry.data));
  230. if (ret < 0) {
  231. fprintf(stderr, "failed to read evt(%d)\n", ret);
  232. return ret;
  233. }
  234. entry.len = ret;
  235. if (entry.data[6] != 0x00) {
  236. DBGPRINT("command failed. status=%02x", entry.data[6]);
  237. ctx->patch_error = 1;
  238. return -1;
  239. }
  240. entry.data[0] = HCI_COMMAND_PKT;
  241. entry.data[1] = 0x05;
  242. entry.data[2] = 0xFC;
  243. entry.data[3] = 0x00;
  244. entry.len = HCI_TYPE_LEN + HCI_COMMAND_HDR_SIZE;
  245. ret = intel_write_cmd(ctx->dev, entry.data, entry.len);
  246. if (ret < 0) {
  247. fprintf(stderr, "failed to send cmd(%d)\n", ret);
  248. return ret;
  249. }
  250. ret = intel_read_evt(ctx->dev, entry.data, sizeof(entry.data));
  251. if (ret < 0) {
  252. fprintf(stderr, "failed to read evt(%d)\n", ret);
  253. return ret;
  254. }
  255. entry.len = ret;
  256. if (entry.data[6] != 0x00) {
  257. DBGPRINT("command failed. status=%02x", entry.data[6]);
  258. ctx->patch_error = 1;
  259. return -1;
  260. }
  261. for (i = 0; i < INTEL_VER_PARAM_LEN; i++)
  262. sprintf(&fw_ver[i*2], "%02x", entry.data[7+i]);
  263. if (open_patch_file(ctx, fw_ver) < 0) {
  264. ctx->patch_error = 1;
  265. return -1;
  266. }
  267. return ret;
  268. }
  269. /*
  270. * check the event is startup event
  271. */
  272. static int is_startup_evt(unsigned char *buf)
  273. {
  274. if (buf[1] == 0xFF && buf[2] == 0x01 && buf[3] == 0x00)
  275. return 1;
  276. return 0;
  277. }
  278. /**
  279. * Finalize the patch process and reset the controller
  280. */
  281. static int post_patch(struct patch_ctx *ctx)
  282. {
  283. int ret;
  284. struct patch_entry entry;
  285. DBGPRINT("start post_patch");
  286. entry.data[0] = HCI_COMMAND_PKT;
  287. entry.data[1] = 0x11;
  288. entry.data[2] = 0xFC;
  289. entry.data[3] = 0x02;
  290. entry.data[4] = 0x00;
  291. if (ctx->reset_enable_patch)
  292. entry.data[5] = 0x02;
  293. else
  294. entry.data[5] = 0x01;
  295. entry.len = HCI_TYPE_LEN + HCI_COMMAND_HDR_SIZE + INTEL_MFG_PARAM_LEN;
  296. ret = intel_write_cmd(ctx->dev, entry.data, entry.len);
  297. if (ret < 0) {
  298. fprintf(stderr, "failed to send cmd(%d)\n", ret);
  299. return ret;
  300. }
  301. ret = intel_read_evt(ctx->dev, entry.data, sizeof(entry.data));
  302. if (ret < 0) {
  303. fprintf(stderr, "failed to read evt(%d)\n", ret);
  304. return ret;
  305. }
  306. entry.len = ret;
  307. if (entry.data[6] != 0x00) {
  308. fprintf(stderr, "cmd failed. st=%02x\n", entry.data[6]);
  309. return -1;
  310. }
  311. do {
  312. ret = intel_read_evt(ctx->dev, entry.data,
  313. sizeof(entry.data));
  314. if (ret < 0) {
  315. fprintf(stderr, "failed to read cmd(%d)\n", ret);
  316. return ret;
  317. }
  318. entry.len = ret;
  319. } while (!is_startup_evt(entry.data));
  320. return ret;
  321. }
  322. /**
  323. * Main routine that handles the device patching process.
  324. */
  325. static int intel_patch_device(struct patch_ctx *ctx)
  326. {
  327. int ret;
  328. ret = pre_patch(ctx);
  329. if (ret < 0) {
  330. if (!ctx->patch_error) {
  331. fprintf(stderr, "I/O error: pre_patch failed\n");
  332. return ret;
  333. }
  334. DBGPRINT("patch failed. proceed to post patch");
  335. goto post_patch;
  336. }
  337. ret = intel_download_patch(ctx);
  338. if (ret < 0) {
  339. if (!ctx->patch_error) {
  340. fprintf(stderr, "I/O error: download_patch failed\n");
  341. close(ctx->fd);
  342. return ret;
  343. }
  344. } else {
  345. DBGPRINT("patch done");
  346. ctx->reset_enable_patch = 1;
  347. }
  348. close(ctx->fd);
  349. post_patch:
  350. ret = post_patch(ctx);
  351. if (ret < 0) {
  352. fprintf(stderr, "post_patch failed(%d)\n", ret);
  353. return ret;
  354. }
  355. return 0;
  356. }
  357. static int set_rts(int dev, int rtsval)
  358. {
  359. int arg;
  360. if (ioctl(dev, TIOCMGET, &arg) < 0) {
  361. perror("cannot get TIOCMGET");
  362. return -errno;
  363. }
  364. if (rtsval)
  365. arg |= TIOCM_RTS;
  366. else
  367. arg &= ~TIOCM_RTS;
  368. if (ioctl(dev, TIOCMSET, &arg) == -1) {
  369. perror("cannot set TIOCMGET");
  370. return -errno;
  371. }
  372. return 0;
  373. }
  374. static unsigned char get_intel_speed(int speed)
  375. {
  376. switch (speed) {
  377. case 9600:
  378. return 0x00;
  379. case 19200:
  380. return 0x01;
  381. case 38400:
  382. return 0x02;
  383. case 57600:
  384. return 0x03;
  385. case 115200:
  386. return 0x04;
  387. case 230400:
  388. return 0x05;
  389. case 460800:
  390. return 0x06;
  391. case 921600:
  392. return 0x07;
  393. case 1843200:
  394. return 0x08;
  395. case 3250000:
  396. return 0x09;
  397. case 2000000:
  398. return 0x0A;
  399. case 3000000:
  400. return 0x0B;
  401. default:
  402. return 0xFF;
  403. }
  404. }
  405. /**
  406. * if it failed to change to new baudrate, it will rollback
  407. * to initial baudrate
  408. */
  409. static int change_baudrate(int dev, int init_speed, int *speed,
  410. struct termios *ti)
  411. {
  412. int ret;
  413. unsigned char br;
  414. unsigned char cmd[5];
  415. unsigned char evt[7];
  416. DBGPRINT("start baudrate change");
  417. ret = set_rts(dev, 0);
  418. if (ret < 0) {
  419. fprintf(stderr, "failed to clear RTS\n");
  420. return ret;
  421. }
  422. cmd[0] = HCI_COMMAND_PKT;
  423. cmd[1] = 0x06;
  424. cmd[2] = 0xFC;
  425. cmd[3] = 0x01;
  426. br = get_intel_speed(*speed);
  427. if (br == 0xFF) {
  428. fprintf(stderr, "speed %d is not supported\n", *speed);
  429. return -1;
  430. }
  431. cmd[4] = br;
  432. ret = intel_write_cmd(dev, cmd, sizeof(cmd));
  433. if (ret < 0) {
  434. fprintf(stderr, "failed to send cmd(%d)\n", ret);
  435. return ret;
  436. }
  437. /*
  438. * wait for buffer to be consumed by the controller
  439. */
  440. usleep(300000);
  441. if (set_speed(dev, ti, *speed) < 0) {
  442. fprintf(stderr, "can't set to new baud rate\n");
  443. return -1;
  444. }
  445. ret = set_rts(dev, 1);
  446. if (ret < 0) {
  447. fprintf(stderr, "failed to set RTS\n");
  448. return ret;
  449. }
  450. ret = intel_read_evt(dev, evt, sizeof(evt));
  451. if (ret < 0) {
  452. fprintf(stderr, "failed to read evt(%d)\n", ret);
  453. return ret;
  454. }
  455. if (evt[4] != 0x00) {
  456. fprintf(stderr,
  457. "failed to change speed. use default speed %d\n",
  458. init_speed);
  459. *speed = init_speed;
  460. }
  461. return 0;
  462. }
  463. /**
  464. * An entry point for Intel specific initialization
  465. */
  466. int intel_init(int dev, int init_speed, int *speed, struct termios *ti)
  467. {
  468. int ret = 0;
  469. struct patch_ctx ctx;
  470. if (change_baudrate(dev, init_speed, speed, ti) < 0)
  471. return -1;
  472. ctx.dev = dev;
  473. ctx.patch_error = 0;
  474. ctx.reset_enable_patch = 0;
  475. ret = intel_patch_device(&ctx);
  476. if (ret < 0)
  477. fprintf(stderr, "failed to initialize the device");
  478. return ret;
  479. }