hciattach_ath3k.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2009-2010 Atheros Communications Inc.
  4. *
  5. */
  6. #ifdef HAVE_CONFIG_H
  7. #include <config.h>
  8. #endif
  9. #define _GNU_SOURCE
  10. #include <stdio.h>
  11. #include <errno.h>
  12. #include <unistd.h>
  13. #include <stdlib.h>
  14. #include <string.h>
  15. #include <ctype.h>
  16. #include <time.h>
  17. #include <sys/stat.h>
  18. #include <sys/time.h>
  19. #include <sys/types.h>
  20. #include <sys/param.h>
  21. #include <sys/ioctl.h>
  22. #include "lib/bluetooth.h"
  23. #include "lib/hci.h"
  24. #include "lib/hci_lib.h"
  25. #include "hciattach.h"
  26. #define TRUE 1
  27. #define FALSE 0
  28. #define FW_PATH "/lib/firmware/ar3k/"
  29. struct ps_cfg_entry {
  30. uint32_t id;
  31. uint32_t len;
  32. uint8_t *data;
  33. };
  34. struct ps_entry_type {
  35. unsigned char type;
  36. unsigned char array;
  37. };
  38. #define MAX_TAGS 50
  39. #define PS_HDR_LEN 4
  40. #define HCI_VENDOR_CMD_OGF 0x3F
  41. #define HCI_PS_CMD_OCF 0x0B
  42. struct ps_cfg_entry ps_list[MAX_TAGS];
  43. static void load_hci_ps_hdr(uint8_t *cmd, uint8_t ps_op, int len, int index)
  44. {
  45. hci_command_hdr *ch = (void *)cmd;
  46. ch->opcode = htobs(cmd_opcode_pack(HCI_VENDOR_CMD_OGF,
  47. HCI_PS_CMD_OCF));
  48. ch->plen = len + PS_HDR_LEN;
  49. cmd += HCI_COMMAND_HDR_SIZE;
  50. cmd[0] = ps_op;
  51. cmd[1] = index;
  52. cmd[2] = index >> 8;
  53. cmd[3] = len;
  54. }
  55. #define PS_EVENT_LEN 100
  56. /*
  57. * Send HCI command and wait for command complete event.
  58. * The event buffer has to be freed by the caller.
  59. */
  60. static int send_hci_cmd_sync(int dev, uint8_t *cmd, int len, uint8_t **event)
  61. {
  62. int err;
  63. uint8_t *hci_event;
  64. uint8_t pkt_type = HCI_COMMAND_PKT;
  65. if (len == 0)
  66. return len;
  67. if (write(dev, &pkt_type, 1) != 1)
  68. return -EILSEQ;
  69. if (write(dev, (unsigned char *)cmd, len) != len)
  70. return -EILSEQ;
  71. hci_event = (uint8_t *)malloc(PS_EVENT_LEN);
  72. if (!hci_event)
  73. return -ENOMEM;
  74. err = read_hci_event(dev, (unsigned char *)hci_event, PS_EVENT_LEN);
  75. if (err > 0) {
  76. *event = hci_event;
  77. } else {
  78. free(hci_event);
  79. return -EILSEQ;
  80. }
  81. return len;
  82. }
  83. #define HCI_EV_SUCCESS 0x00
  84. static int read_ps_event(uint8_t *event, uint16_t ocf)
  85. {
  86. hci_event_hdr *eh;
  87. uint16_t opcode = htobs(cmd_opcode_pack(HCI_VENDOR_CMD_OGF, ocf));
  88. event++;
  89. eh = (void *)event;
  90. event += HCI_EVENT_HDR_SIZE;
  91. if (eh->evt == EVT_CMD_COMPLETE) {
  92. evt_cmd_complete *cc = (void *)event;
  93. event += EVT_CMD_COMPLETE_SIZE;
  94. if (cc->opcode == opcode && event[0] == HCI_EV_SUCCESS)
  95. return 0;
  96. else
  97. return -EILSEQ;
  98. }
  99. return -EILSEQ;
  100. }
  101. static int write_cmd(int fd, uint8_t *buffer, int len)
  102. {
  103. uint8_t *event;
  104. int err;
  105. err = send_hci_cmd_sync(fd, buffer, len, &event);
  106. if (err < 0)
  107. return err;
  108. err = read_ps_event(event, HCI_PS_CMD_OCF);
  109. free(event);
  110. return err;
  111. }
  112. #define PS_WRITE 1
  113. #define PS_RESET 2
  114. #define WRITE_PATCH 8
  115. #define ENABLE_PATCH 11
  116. #define HCI_PS_CMD_HDR_LEN 7
  117. #define PS_RESET_PARAM_LEN 6
  118. #define HCI_MAX_CMD_SIZE 260
  119. #define PS_RESET_CMD_LEN (HCI_PS_CMD_HDR_LEN + PS_RESET_PARAM_LEN)
  120. #define PS_ID_MASK 0xFF
  121. /* Sends PS commands using vendor specficic HCI commands */
  122. static int write_ps_cmd(int fd, uint8_t opcode, uint32_t ps_param)
  123. {
  124. uint8_t cmd[HCI_MAX_CMD_SIZE];
  125. uint32_t i;
  126. switch (opcode) {
  127. case ENABLE_PATCH:
  128. load_hci_ps_hdr(cmd, opcode, 0, 0x00);
  129. if (write_cmd(fd, cmd, HCI_PS_CMD_HDR_LEN) < 0)
  130. return -EILSEQ;
  131. break;
  132. case PS_RESET:
  133. load_hci_ps_hdr(cmd, opcode, PS_RESET_PARAM_LEN, 0x00);
  134. cmd[7] = 0x00;
  135. cmd[PS_RESET_CMD_LEN - 2] = ps_param & PS_ID_MASK;
  136. cmd[PS_RESET_CMD_LEN - 1] = (ps_param >> 8) & PS_ID_MASK;
  137. if (write_cmd(fd, cmd, PS_RESET_CMD_LEN) < 0)
  138. return -EILSEQ;
  139. break;
  140. case PS_WRITE:
  141. for (i = 0; i < ps_param; i++) {
  142. load_hci_ps_hdr(cmd, opcode, ps_list[i].len,
  143. ps_list[i].id);
  144. memcpy(&cmd[HCI_PS_CMD_HDR_LEN], ps_list[i].data,
  145. ps_list[i].len);
  146. if (write_cmd(fd, cmd, ps_list[i].len +
  147. HCI_PS_CMD_HDR_LEN) < 0)
  148. return -EILSEQ;
  149. }
  150. break;
  151. }
  152. return 0;
  153. }
  154. #define __is_delim(ch) ((ch) == ':')
  155. #define MAX_PREAMBLE_LEN 4
  156. /* Parse PS entry preamble of format [X:X] for main type and subtype */
  157. static int get_ps_type(char *ptr, int index, char *type, char *sub_type)
  158. {
  159. int i;
  160. int delim = FALSE;
  161. if (index > MAX_PREAMBLE_LEN)
  162. return -EILSEQ;
  163. for (i = 1; i < index; i++) {
  164. if (__is_delim(ptr[i])) {
  165. delim = TRUE;
  166. continue;
  167. }
  168. if (isalpha(ptr[i])) {
  169. if (delim == FALSE)
  170. (*type) = toupper(ptr[i]);
  171. else
  172. (*sub_type) = toupper(ptr[i]);
  173. }
  174. }
  175. return 0;
  176. }
  177. #define ARRAY 'A'
  178. #define STRING 'S'
  179. #define DECIMAL 'D'
  180. #define BINARY 'B'
  181. #define PS_HEX 0
  182. #define PS_DEC 1
  183. static int get_input_format(char *buf, struct ps_entry_type *format)
  184. {
  185. char *ptr = NULL;
  186. char type = '\0';
  187. char sub_type = '\0';
  188. format->type = PS_HEX;
  189. format->array = TRUE;
  190. if (strstr(buf, "[") != buf)
  191. return 0;
  192. ptr = strstr(buf, "]");
  193. if (!ptr)
  194. return -EILSEQ;
  195. if (get_ps_type(buf, ptr - buf, &type, &sub_type) < 0)
  196. return -EILSEQ;
  197. /* Check is data type is of array */
  198. if (type == ARRAY || sub_type == ARRAY)
  199. format->array = TRUE;
  200. if (type == STRING || sub_type == STRING)
  201. format->array = FALSE;
  202. if (type == DECIMAL || type == BINARY)
  203. format->type = PS_DEC;
  204. else
  205. format->type = PS_HEX;
  206. return 0;
  207. }
  208. #define UNDEFINED 0xFFFF
  209. static unsigned int read_data_in_section(char *buf, struct ps_entry_type type)
  210. {
  211. char *ptr = buf;
  212. if (!buf)
  213. return UNDEFINED;
  214. if (buf == strstr(buf, "[")) {
  215. ptr = strstr(buf, "]");
  216. if (!ptr)
  217. return UNDEFINED;
  218. ptr++;
  219. }
  220. if (type.type == PS_HEX && type.array != TRUE)
  221. return strtol(ptr, NULL, 16);
  222. return UNDEFINED;
  223. }
  224. struct tag_info {
  225. unsigned section;
  226. unsigned line_count;
  227. unsigned char_cnt;
  228. unsigned byte_count;
  229. };
  230. static inline int update_char_count(const char *buf)
  231. {
  232. char *end_ptr;
  233. if (strstr(buf, "[") == buf) {
  234. end_ptr = strstr(buf, "]");
  235. if (!end_ptr)
  236. return 0;
  237. else
  238. return (end_ptr - buf) + 1;
  239. }
  240. return 0;
  241. }
  242. /* Read PS entries as string, convert and add to Hex array */
  243. static void update_tag_data(struct ps_cfg_entry *tag,
  244. struct tag_info *info, const char *ptr)
  245. {
  246. char buf[3];
  247. buf[2] = '\0';
  248. strncpy(buf, &ptr[info->char_cnt], 2);
  249. tag->data[info->byte_count] = strtol(buf, NULL, 16);
  250. info->char_cnt += 3;
  251. info->byte_count++;
  252. strncpy(buf, &ptr[info->char_cnt], 2);
  253. tag->data[info->byte_count] = strtol(buf, NULL, 16);
  254. info->char_cnt += 3;
  255. info->byte_count++;
  256. }
  257. #define PS_UNDEF 0
  258. #define PS_ID 1
  259. #define PS_LEN 2
  260. #define PS_DATA 3
  261. #define PS_MAX_LEN 500
  262. #define LINE_SIZE_MAX (PS_MAX_LEN * 2)
  263. #define ENTRY_PER_LINE 16
  264. #define __check_comment(buf) (((buf)[0] == '/') && ((buf)[1] == '/'))
  265. #define __skip_space(str) while (*(str) == ' ') ((str)++)
  266. static int ath_parse_ps(FILE *stream)
  267. {
  268. char buf[LINE_SIZE_MAX + 1];
  269. char *ptr;
  270. uint8_t tag_cnt = 0;
  271. int16_t byte_count = 0;
  272. struct ps_entry_type format;
  273. struct tag_info status = { 0, 0, 0, 0 };
  274. do {
  275. int read_count;
  276. struct ps_cfg_entry *tag;
  277. ptr = fgets(buf, LINE_SIZE_MAX, stream);
  278. if (!ptr)
  279. break;
  280. __skip_space(ptr);
  281. if (__check_comment(ptr))
  282. continue;
  283. /* Lines with a '#' will be followed by new PS entry */
  284. if (ptr == strstr(ptr, "#")) {
  285. if (status.section != PS_UNDEF) {
  286. return -EILSEQ;
  287. } else {
  288. status.section = PS_ID;
  289. continue;
  290. }
  291. }
  292. tag = &ps_list[tag_cnt];
  293. switch (status.section) {
  294. case PS_ID:
  295. if (get_input_format(ptr, &format) < 0)
  296. return -EILSEQ;
  297. tag->id = read_data_in_section(ptr, format);
  298. status.section = PS_LEN;
  299. break;
  300. case PS_LEN:
  301. if (get_input_format(ptr, &format) < 0)
  302. return -EILSEQ;
  303. byte_count = read_data_in_section(ptr, format);
  304. if (byte_count > PS_MAX_LEN)
  305. return -EILSEQ;
  306. tag->len = byte_count;
  307. tag->data = (uint8_t *)malloc(byte_count);
  308. status.section = PS_DATA;
  309. status.line_count = 0;
  310. break;
  311. case PS_DATA:
  312. if (status.line_count == 0)
  313. if (get_input_format(ptr, &format) < 0)
  314. return -EILSEQ;
  315. __skip_space(ptr);
  316. status.char_cnt = update_char_count(ptr);
  317. read_count = (byte_count > ENTRY_PER_LINE) ?
  318. ENTRY_PER_LINE : byte_count;
  319. if (format.type == PS_HEX && format.array == TRUE) {
  320. while (read_count > 0) {
  321. update_tag_data(tag, &status, ptr);
  322. read_count -= 2;
  323. }
  324. if (byte_count > ENTRY_PER_LINE)
  325. byte_count -= ENTRY_PER_LINE;
  326. else
  327. byte_count = 0;
  328. }
  329. status.line_count++;
  330. if (byte_count == 0)
  331. memset(&status, 0x00, sizeof(struct tag_info));
  332. if (status.section == PS_UNDEF)
  333. tag_cnt++;
  334. if (tag_cnt == MAX_TAGS)
  335. return -EILSEQ;
  336. break;
  337. }
  338. } while (ptr);
  339. return tag_cnt;
  340. }
  341. #define MAX_PATCH_CMD 244
  342. struct patch_entry {
  343. int16_t len;
  344. uint8_t data[MAX_PATCH_CMD];
  345. };
  346. #define SET_PATCH_RAM_ID 0x0D
  347. #define SET_PATCH_RAM_CMD_SIZE 11
  348. #define ADDRESS_LEN 4
  349. static int set_patch_ram(int dev, char *patch_loc, int len)
  350. {
  351. int err;
  352. uint8_t cmd[20];
  353. int i, j;
  354. char loc_byte[3];
  355. uint8_t *event;
  356. uint8_t *loc_ptr = &cmd[7];
  357. if (!patch_loc)
  358. return -1;
  359. loc_byte[2] = '\0';
  360. load_hci_ps_hdr(cmd, SET_PATCH_RAM_ID, ADDRESS_LEN, 0);
  361. for (i = 0, j = 3; i < 4; i++, j--) {
  362. loc_byte[0] = patch_loc[0];
  363. loc_byte[1] = patch_loc[1];
  364. loc_ptr[j] = strtol(loc_byte, NULL, 16);
  365. patch_loc += 2;
  366. }
  367. err = send_hci_cmd_sync(dev, cmd, SET_PATCH_RAM_CMD_SIZE, &event);
  368. if (err < 0)
  369. return err;
  370. err = read_ps_event(event, HCI_PS_CMD_OCF);
  371. free(event);
  372. return err;
  373. }
  374. #define PATCH_LOC_KEY "DA:"
  375. #define PATCH_LOC_STRING_LEN (8 + 237)
  376. static int ps_patch_download(int fd, FILE *stream)
  377. {
  378. char byte[3];
  379. char ptr[MAX_PATCH_CMD + 1];
  380. int byte_cnt;
  381. int patch_count = 0;
  382. char patch_loc[PATCH_LOC_STRING_LEN + 1];
  383. byte[2] = '\0';
  384. while (fgets(ptr, MAX_PATCH_CMD, stream)) {
  385. if (strlen(ptr) <= 1)
  386. continue;
  387. else if (strstr(ptr, PATCH_LOC_KEY) == ptr) {
  388. strncpy(patch_loc, &ptr[sizeof(PATCH_LOC_KEY) - 1],
  389. PATCH_LOC_STRING_LEN);
  390. if (set_patch_ram(fd, patch_loc, sizeof(patch_loc)) < 0)
  391. return -1;
  392. } else if (isxdigit(ptr[0]))
  393. break;
  394. else
  395. return -1;
  396. }
  397. byte_cnt = strtol(ptr, NULL, 16);
  398. while (byte_cnt > 0) {
  399. int i;
  400. uint8_t cmd[HCI_MAX_CMD_SIZE];
  401. struct patch_entry patch;
  402. if (byte_cnt > MAX_PATCH_CMD)
  403. patch.len = MAX_PATCH_CMD;
  404. else
  405. patch.len = byte_cnt;
  406. for (i = 0; i < patch.len; i++) {
  407. if (!fgets(byte, 3, stream))
  408. return -1;
  409. patch.data[i] = strtoul(byte, NULL, 16);
  410. }
  411. load_hci_ps_hdr(cmd, WRITE_PATCH, patch.len, patch_count);
  412. memcpy(&cmd[HCI_PS_CMD_HDR_LEN], patch.data, patch.len);
  413. if (write_cmd(fd, cmd, patch.len + HCI_PS_CMD_HDR_LEN) < 0)
  414. return -1;
  415. patch_count++;
  416. byte_cnt = byte_cnt - MAX_PATCH_CMD;
  417. }
  418. if (write_ps_cmd(fd, ENABLE_PATCH, 0) < 0)
  419. return -1;
  420. return patch_count;
  421. }
  422. #define PS_RAM_SIZE 2048
  423. static int ps_config_download(int fd, int tag_count)
  424. {
  425. if (write_ps_cmd(fd, PS_RESET, PS_RAM_SIZE) < 0)
  426. return -1;
  427. if (tag_count > 0)
  428. if (write_ps_cmd(fd, PS_WRITE, tag_count) < 0)
  429. return -1;
  430. return 0;
  431. }
  432. #define PS_ASIC_FILE_PREFIX "PS_ASIC"
  433. #define PS_FPGA_FILE_PREFIX "PS_FPGA"
  434. static void get_ps_file_name(uint32_t devtype, uint32_t rom_version, char *path,
  435. char *region)
  436. {
  437. char *file_prefix;
  438. struct stat st;
  439. if (devtype == 0xdeadc0de)
  440. file_prefix = PS_ASIC_FILE_PREFIX;
  441. else
  442. file_prefix = PS_FPGA_FILE_PREFIX;
  443. if (!region)
  444. goto default_ps_file;
  445. snprintf(path, MAXPATHLEN, "%s%x/%s-%s.pst", FW_PATH, rom_version,
  446. file_prefix, region);
  447. if (stat(path, &st) == 0)
  448. return;
  449. perror("PS file with region code not exist, use default PS file\n");
  450. default_ps_file:
  451. snprintf(path, MAXPATHLEN, "%s%x/%s.pst", FW_PATH, rom_version,
  452. file_prefix);
  453. }
  454. #define PATCH_FILE "RamPatch.txt"
  455. #define FPGA_ROM_VERSION 0x99999999
  456. #define ROM_DEV_TYPE 0xdeadc0de
  457. static void get_patch_file_name(uint32_t dev_type, uint32_t rom_version,
  458. uint32_t build_version, char *path)
  459. {
  460. if (rom_version == FPGA_ROM_VERSION && dev_type != ROM_DEV_TYPE &&
  461. dev_type != 0 && build_version == 1)
  462. path[0] = '\0';
  463. else
  464. snprintf(path, MAXPATHLEN, "%s%x/%s",
  465. FW_PATH, rom_version, PATCH_FILE);
  466. }
  467. #define VERIFY_CRC 9
  468. #define PS_REGION 1
  469. #define PATCH_REGION 2
  470. static int get_ath3k_crc(int dev)
  471. {
  472. uint8_t cmd[7];
  473. uint8_t *event;
  474. int err;
  475. load_hci_ps_hdr(cmd, VERIFY_CRC, 0, PS_REGION | PATCH_REGION);
  476. err = send_hci_cmd_sync(dev, cmd, sizeof(cmd), &event);
  477. if (err < 0)
  478. return err;
  479. /* Send error code if CRC check patched */
  480. if (read_ps_event(event, HCI_PS_CMD_OCF) >= 0)
  481. err = -EILSEQ;
  482. free(event);
  483. return err;
  484. }
  485. #define DEV_REGISTER 0x4FFC
  486. #define GET_DEV_TYPE_OCF 0x05
  487. static int get_device_type(int dev, uint32_t *code)
  488. {
  489. uint8_t cmd[8];
  490. uint8_t *event;
  491. uint32_t reg;
  492. int err;
  493. uint8_t *ptr = cmd;
  494. hci_command_hdr *ch = (void *)cmd;
  495. ch->opcode = htobs(cmd_opcode_pack(HCI_VENDOR_CMD_OGF,
  496. GET_DEV_TYPE_OCF));
  497. ch->plen = 5;
  498. ptr += HCI_COMMAND_HDR_SIZE;
  499. ptr[0] = (uint8_t)DEV_REGISTER;
  500. ptr[1] = (uint8_t)DEV_REGISTER >> 8;
  501. ptr[2] = (uint8_t)DEV_REGISTER >> 16;
  502. ptr[3] = (uint8_t)DEV_REGISTER >> 24;
  503. ptr[4] = 0x04;
  504. err = send_hci_cmd_sync(dev, cmd, sizeof(cmd), &event);
  505. if (err < 0)
  506. return err;
  507. err = read_ps_event(event, GET_DEV_TYPE_OCF);
  508. if (err < 0)
  509. goto cleanup;
  510. reg = event[10];
  511. reg = (reg << 8) | event[9];
  512. reg = (reg << 8) | event[8];
  513. reg = (reg << 8) | event[7];
  514. *code = reg;
  515. cleanup:
  516. free(event);
  517. return err;
  518. }
  519. #define GET_VERSION_OCF 0x1E
  520. static int read_ath3k_version(int pConfig, uint32_t *rom_version,
  521. uint32_t *build_version)
  522. {
  523. uint8_t cmd[3];
  524. uint8_t *event;
  525. int err;
  526. int status;
  527. hci_command_hdr *ch = (void *)cmd;
  528. ch->opcode = htobs(cmd_opcode_pack(HCI_VENDOR_CMD_OGF,
  529. GET_VERSION_OCF));
  530. ch->plen = 0;
  531. err = send_hci_cmd_sync(pConfig, cmd, sizeof(cmd), &event);
  532. if (err < 0)
  533. return err;
  534. err = read_ps_event(event, GET_VERSION_OCF);
  535. if (err < 0)
  536. goto cleanup;
  537. status = event[10];
  538. status = (status << 8) | event[9];
  539. status = (status << 8) | event[8];
  540. status = (status << 8) | event[7];
  541. *rom_version = status;
  542. status = event[14];
  543. status = (status << 8) | event[13];
  544. status = (status << 8) | event[12];
  545. status = (status << 8) | event[11];
  546. *build_version = status;
  547. cleanup:
  548. free(event);
  549. return err;
  550. }
  551. static void convert_bdaddr(char *str_bdaddr, char *bdaddr)
  552. {
  553. char bdbyte[3];
  554. char *str_byte = str_bdaddr;
  555. int i, j;
  556. int colon_present = 0;
  557. if (strstr(str_bdaddr, ":"))
  558. colon_present = 1;
  559. bdbyte[2] = '\0';
  560. /* Reverse the BDADDR to LSB first */
  561. for (i = 0, j = 5; i < 6; i++, j--) {
  562. bdbyte[0] = str_byte[0];
  563. bdbyte[1] = str_byte[1];
  564. bdaddr[j] = strtol(bdbyte, NULL, 16);
  565. if (colon_present == 1)
  566. str_byte += 3;
  567. else
  568. str_byte += 2;
  569. }
  570. }
  571. static int write_bdaddr(int pConfig, char *bdaddr)
  572. {
  573. uint8_t *event;
  574. int err;
  575. uint8_t cmd[13];
  576. uint8_t *ptr = cmd;
  577. hci_command_hdr *ch = (void *)cmd;
  578. memset(cmd, 0, sizeof(cmd));
  579. ch->opcode = htobs(cmd_opcode_pack(HCI_VENDOR_CMD_OGF,
  580. HCI_PS_CMD_OCF));
  581. ch->plen = 10;
  582. ptr += HCI_COMMAND_HDR_SIZE;
  583. ptr[0] = 0x01;
  584. ptr[1] = 0x01;
  585. ptr[2] = 0x00;
  586. ptr[3] = 0x06;
  587. convert_bdaddr(bdaddr, (char *)&ptr[4]);
  588. err = send_hci_cmd_sync(pConfig, cmd, sizeof(cmd), &event);
  589. if (err < 0)
  590. return err;
  591. err = read_ps_event(event, HCI_PS_CMD_OCF);
  592. free(event);
  593. return err;
  594. }
  595. #define BDADDR_FILE "ar3kbdaddr.pst"
  596. static void write_bdaddr_from_file(int rom_version, int fd)
  597. {
  598. FILE *stream;
  599. char bdaddr[PATH_MAX];
  600. char bdaddr_file[PATH_MAX];
  601. snprintf(bdaddr_file, MAXPATHLEN, "%s%x/%s",
  602. FW_PATH, rom_version, BDADDR_FILE);
  603. stream = fopen(bdaddr_file, "r");
  604. if (!stream)
  605. return;
  606. if (fgets(bdaddr, PATH_MAX - 1, stream))
  607. write_bdaddr(fd, bdaddr);
  608. fclose(stream);
  609. }
  610. static int ath_ps_download(int fd)
  611. {
  612. int err = 0;
  613. int tag_count;
  614. int patch_count = 0;
  615. uint32_t rom_version = 0;
  616. uint32_t build_version = 0;
  617. uint32_t dev_type = 0;
  618. char patch_file[PATH_MAX];
  619. char ps_file[PATH_MAX];
  620. FILE *stream;
  621. /*
  622. * Verfiy firmware version. depending on it select the PS
  623. * config file to download.
  624. */
  625. if (get_device_type(fd, &dev_type) < 0) {
  626. err = -EILSEQ;
  627. goto download_cmplete;
  628. }
  629. if (read_ath3k_version(fd, &rom_version, &build_version) < 0) {
  630. err = -EILSEQ;
  631. goto download_cmplete;
  632. }
  633. /* Do not download configuration if CRC passes */
  634. if (get_ath3k_crc(fd) < 0) {
  635. err = 0;
  636. goto download_cmplete;
  637. }
  638. get_ps_file_name(dev_type, rom_version, ps_file, NULL);
  639. get_patch_file_name(dev_type, rom_version, build_version, patch_file);
  640. stream = fopen(ps_file, "r");
  641. if (!stream) {
  642. perror("firmware file open error\n");
  643. err = -EILSEQ;
  644. goto download_cmplete;
  645. }
  646. tag_count = ath_parse_ps(stream);
  647. fclose(stream);
  648. if (tag_count < 0) {
  649. err = -EILSEQ;
  650. goto download_cmplete;
  651. }
  652. stream = fopen(patch_file, "r");
  653. if(stream) {
  654. patch_count = ps_patch_download(fd, stream);
  655. fclose(stream);
  656. if (patch_count < 0) {
  657. err = -EILSEQ;
  658. goto download_cmplete;
  659. }
  660. }
  661. err = ps_config_download(fd, tag_count);
  662. download_cmplete:
  663. if (!err)
  664. write_bdaddr_from_file(rom_version, fd);
  665. return err;
  666. }
  667. #define HCI_SLEEP_CMD_OCF 0x04
  668. /*
  669. * Atheros AR300x specific initialization post callback
  670. */
  671. int ath3k_post(int fd, int pm)
  672. {
  673. int dev_id, dd;
  674. struct timespec tm = { 0, 50000 };
  675. sleep(1);
  676. dev_id = ioctl(fd, HCIUARTGETDEVICE, 0);
  677. if (dev_id < 0) {
  678. perror("cannot get device id");
  679. return dev_id;
  680. }
  681. dd = hci_open_dev(dev_id);
  682. if (dd < 0) {
  683. perror("HCI device open failed");
  684. return dd;
  685. }
  686. if (ioctl(dd, HCIDEVUP, dev_id) < 0 && errno != EALREADY) {
  687. perror("hci down:Power management Disabled");
  688. hci_close_dev(dd);
  689. return -1;
  690. }
  691. /* send vendor specific command with Sleep feature Enabled */
  692. if (hci_send_cmd(dd, OGF_VENDOR_CMD, HCI_SLEEP_CMD_OCF, 1, &pm) < 0)
  693. perror("PM command failed, power management Disabled");
  694. nanosleep(&tm, NULL);
  695. hci_close_dev(dd);
  696. return 0;
  697. }
  698. #define HCI_VENDOR_CMD_OGF 0x3F
  699. #define HCI_PS_CMD_OCF 0x0B
  700. #define HCI_CHG_BAUD_CMD_OCF 0x0C
  701. #define WRITE_BDADDR_CMD_LEN 14
  702. #define WRITE_BAUD_CMD_LEN 6
  703. #define MAX_CMD_LEN WRITE_BDADDR_CMD_LEN
  704. static int set_cntrlr_baud(int fd, int speed)
  705. {
  706. int baud;
  707. struct timespec tm = { 0, 500000 };
  708. unsigned char cmd[MAX_CMD_LEN], rsp[HCI_MAX_EVENT_SIZE];
  709. unsigned char *ptr = cmd + 1;
  710. hci_command_hdr *ch = (void *)ptr;
  711. cmd[0] = HCI_COMMAND_PKT;
  712. /* set controller baud rate to user specified value */
  713. ptr = cmd + 1;
  714. ch->opcode = htobs(cmd_opcode_pack(HCI_VENDOR_CMD_OGF,
  715. HCI_CHG_BAUD_CMD_OCF));
  716. ch->plen = 2;
  717. ptr += HCI_COMMAND_HDR_SIZE;
  718. baud = speed/100;
  719. ptr[0] = (char)baud;
  720. ptr[1] = (char)(baud >> 8);
  721. if (write(fd, cmd, WRITE_BAUD_CMD_LEN) != WRITE_BAUD_CMD_LEN) {
  722. perror("Failed to write change baud rate command");
  723. return -ETIMEDOUT;
  724. }
  725. nanosleep(&tm, NULL);
  726. if (read_hci_event(fd, rsp, sizeof(rsp)) < 0)
  727. return -ETIMEDOUT;
  728. return 0;
  729. }
  730. /*
  731. * Atheros AR300x specific initialization and configuration file
  732. * download
  733. */
  734. int ath3k_init(int fd, int speed, int init_speed, char *bdaddr,
  735. struct termios *ti)
  736. {
  737. int r;
  738. int err = 0;
  739. struct timespec tm = { 0, 500000 };
  740. unsigned char cmd[MAX_CMD_LEN], rsp[HCI_MAX_EVENT_SIZE];
  741. unsigned char *ptr = cmd + 1;
  742. hci_command_hdr *ch = (void *)ptr;
  743. cmd[0] = HCI_COMMAND_PKT;
  744. /* set both controller and host baud rate to maximum possible value */
  745. err = set_cntrlr_baud(fd, speed);
  746. if (err < 0)
  747. return err;
  748. err = set_speed(fd, ti, speed);
  749. if (err < 0) {
  750. perror("Can't set required baud rate");
  751. return err;
  752. }
  753. /* Download PS and patch */
  754. r = ath_ps_download(fd);
  755. if (r < 0) {
  756. perror("Failed to Download configuration");
  757. err = -ETIMEDOUT;
  758. goto failed;
  759. }
  760. /* Write BDADDR */
  761. if (bdaddr) {
  762. ch->opcode = htobs(cmd_opcode_pack(HCI_VENDOR_CMD_OGF,
  763. HCI_PS_CMD_OCF));
  764. ch->plen = 10;
  765. ptr += HCI_COMMAND_HDR_SIZE;
  766. ptr[0] = 0x01;
  767. ptr[1] = 0x01;
  768. ptr[2] = 0x00;
  769. ptr[3] = 0x06;
  770. str2ba(bdaddr, (bdaddr_t *)(ptr + 4));
  771. if (write(fd, cmd, WRITE_BDADDR_CMD_LEN) !=
  772. WRITE_BDADDR_CMD_LEN) {
  773. perror("Failed to write BD_ADDR command\n");
  774. err = -ETIMEDOUT;
  775. goto failed;
  776. }
  777. if (read_hci_event(fd, rsp, sizeof(rsp)) < 0) {
  778. perror("Failed to set BD_ADDR\n");
  779. err = -ETIMEDOUT;
  780. goto failed;
  781. }
  782. }
  783. /* Send HCI Reset */
  784. cmd[1] = 0x03;
  785. cmd[2] = 0x0C;
  786. cmd[3] = 0x00;
  787. r = write(fd, cmd, 4);
  788. if (r != 4) {
  789. err = -ETIMEDOUT;
  790. goto failed;
  791. }
  792. nanosleep(&tm, NULL);
  793. if (read_hci_event(fd, rsp, sizeof(rsp)) < 0) {
  794. err = -ETIMEDOUT;
  795. goto failed;
  796. }
  797. err = set_cntrlr_baud(fd, speed);
  798. if (err < 0)
  799. return err;
  800. failed:
  801. if (err < 0) {
  802. set_cntrlr_baud(fd, init_speed);
  803. set_speed(fd, ti, init_speed);
  804. }
  805. return err;
  806. }